View ML610Q304_8153953.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

fedl610q304-01 issue date: jul 16, 2014 ML610Q304 8-bit microcontroller with voice output function 1/28 general description equipped with a 8-bit cpu nx-u8/100, the ML610Q304 is a high-performance 8-bit cmos microcontroller that integrates a wide variety of peripherals such as timer, synchronous serial port, and voice output function. the nx-u8/100 cpu is capable of executing instructions efficiently on a one-instruction-per-clock-pulse basis through parallel processing by the 3-stage pipelined architecture. the ML610Q304 is also equipped with a flash memory that has achieved low voltage and low power consumption (at read) equivalent to mask roms, so it is best suited to battery-driven applications such as alarm and portable devices. in addition, it has an on-chip debugging function, which allows software debugging/rewriting with the lsi mounted on the board. features ? cpu ? 8-bit risc cpu (cpu name: nx-u8/100) ? instruction system: 16-bit instructions ? instruction set: transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on ? on-chip debug function ? minimum instruction execution time approx 30.5 s (@32.768khz system clock) approx 0.244 s (@4.096 mhz system clock)@v dd =2.0 to 5.5v approx 0.122 s (@8.192 mhz system clock)@v dd =2.2 to 5.5v ? internal memory ? has 96-kbyte flash rom(48k 16-bits) built in. (1 k byte of test domain that it cannot be used is included) ? has 2-kbyte flash rom built in. (area in which self rewriting is possible (512byte 4)) ? internal 1kbyte ram (1k 8 bits) ? interrupt controller ? 2 non-maskable interrupt sources (inte rnal source: 1, external source: 1) ? 24 maskable interrupt sources (internal source: 16, external source: 8) ? time base counter ? low-speed time base counter 1 channel ? high-speed time base counter 1 channel ? watchdog timer ? generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second ? free running ? overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) ? timers ? 8 bits 4ch (16-bit configuration available) ? voice output function ? voice synthesis method: 4-bit adpcm2 / non-linear pcm / straight 8-bit pcm / straight 16-bit pcm ? sampling frequency: 8/16/32 khz; 10.7/21.3 khz; 6.4/12.8/25.6 khz
fedl610q304-01 ML610Q304 2/28 ? successive approximation type a/d converter ? 10-bit a/d converter ? input: 3ch (ch0-2:external input) ? conversion time: 24.4 s per channel at 4.096mhz v dd R 2.2v ? conversion time: 12.2 s per channel at 8.192mhz v dd R 2.5v ? synchronous serial port ? 2ch ? master/slave selectable ? lsb first/msb first selectable ? 8-bit length/16-bit length selectable ? uart ? half-duplex 1ch ? txd/rxd ? bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits ? positive logic/negative logic selectable ? built-in baud rate generator ? i 2 c bus interface ? slave function and master function ? fast mode (400 kbps), standard mode (100 kbps) ? general-purpose ports ? input-only port 1ch ? output-only port 3ch (including secondary functions) ? input/output 11ch (including secondary functions)(p40 to p42 uses also as an a/d converter input port.) ? speaker amplifier(d-class) output power ? 1.0w(at 5.0v)/0.45w(at 3.0v) ? disconnection detection circuit ? speaker pin short detection circuit ? pll oscillation stop detection reset ? reset ? reset through the reset_n pin ? power-on reset generation when powered on ? reset by the watchdog timer (wdt) overflow ? pll oscillation stop detection reset ? clock ? low-speed clock built-in rc oscillation (32.768 khz) ? high-speed clock built-in pll oscillation (4.096mhz,8.192mhz,etc)
fedl610q304-01 ML610Q304 3/28 ? power management ? stop mode: stop of oscillation (operations of cpu and peripheral circuits are stopped.) ? halt mode: instruction execution by cpu is suspended (peripheral circuits are in operating states). ? clock gear: the frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) ? block control function: operation of an intact functional block circuit is powerd down. (register reset and clock stop) ? shipment ? 28-pin qfn ML610Q304-xxxgd (blank product: ML610Q304-nnngd) xxx: rom code number ? guaranteed operating range ? operating temperature: ? 40 c to 85 c ? operating voltage: v dd = 2.0v to 5.5v, spv dd = 2.0v to 5.5v
fedl610q304-01 ML610Q304 4/28 block diagram figure 1 is a block diagram of the ML610Q304. * : secondary or tertiary function *1: i/o port or a/d converter input terminal figure 1-1 block diagram of ML610Q304 program memory flash 96kbyte ram 1kbyte interrupt controller cpu (nx-u8/100) timing controller ea sp instruction decoder bus controller instruction register tbc int 4 int 4 8bit timer data-bus test reset_n osc power v ddl reset & test alu epsw1 3 psw elr1 3 lr ecsr1 3 dsr/csr pc greg 0 15 v dd v ss on-chip ice ssio sck0* sin0* sout0* int 2 wdt int 1 int 2 10bit-adc ain0 to ain2 * 1 v ref 1 int lsclk* outclk* voicecnt sck1* sin1* sout1* spp spm p80 to p87 gpio nmi p20 to p22 int 9 p40 to p42 *1 i 2 c master/slave int 2 sda* scl* 50 to p57 spv dd spv ss d-class speaker amplifier uart int 1 rxd0* txd0*
fedl610q304-01 ML610Q304 5/28 pin configuration ML610Q304 qfn package product (top view) (nc): no connection figure 1-2 pin layout of ML610Q304 package p22/led2 1 v ss 3 p20/led0 4 p80/exi0/sda/sin0 5 p81/exi1/scl/sck0 6 test1_n 7 8 test0 9 p82/exi2/sout0 13 spm 12 spp 11 reset_n 10 p83/exi3 14 (nc) nmi 28 p87/exi7/txd0 27 p41/ain1 23 p40/ain0 24 v ref 25 p86/exi6/rxd0/sout1 26 p42/ain2 22 21 v dd 20 v ddl 19 v ss 18 p85/exi5/sck1 17 p84/exi4/sin1 16 spv dd 15 spv ss p21/led1 2
fedl610q304-01 ML610Q304 6/28 list of pins in the i/o column, ??? denotes an input pin (for primary functions only), ?i? an input pin, ?o? an output pin, and ?i/o? an input/output pin. primary function secondary function tertiary function pad no pin name i/o description pin name i/o description pin name i/o description 12 spp o positive output pin of the built-in speaker amplifier ? ? ? ? ? ? 13 spm o negative output pin of the built-in speaker amplifier ? ? ? ? ? ? 15 spv ss ? negative power supply pin for built-in speaker amplifier ? ? ? ? ? ? 16 spv dd ? positive power supply pin for built-in speaker amplifier ? ? ? ? ? ? 3 v ss ? negative power supply pin ? ? ? ? ? ? 19 v ss ? negative power supply pin ? ? ? ? ? ? 20 v ddl ? power supply for internal logic (internally generated) ? ? ? ? ? ? 21 v dd ? positive power supply pin ? ? ? ? ? ? 25 v ref ? reference power supply pin for successive-approxima tion type adc ? ? ? ? ? ? 11 reset_n i reset input pin ? ? ? ? ? ? 8 test0 i/o input/output pin for testing ? ? ? ? ? ? 7 test1_n i input pin for testing ? ? ? ? ? ? 28 nmi i input port, non-maskable interrupt ? ? ? ? ? ? 4 p20/led0 o output port / led port lsclk o low-speed clock output ? ? ? 2 p21/led1 o output port / led port outclk o high-speed clock output ? ? ? 1 p22/led2 o output port / led port ? ? ? ? ? ? 24 p40/ain0 i/o input port/output port /successive-approxi mation type adc input ? ? ? sin0 i ssio0 data input 23 p41/ain1 i/o input port/output port /successive-approxi mation type adc input ? ? ? sck0 i/o ssio0 synchronous clock input/output 22 p42/ain2 i/o input port/output port /successive-approxi mation type adc input ? ? ? sout0 o ssio0 data output 5 p80/exi0 i/o input port/output port / external interrupt sda i/o i 2 c synchronous data input/output sin0 i ssio0 data input
fedl610q304-01 ML610Q304 7/28 primary function secondary function tertiary function pad no pin name i/o description pin name i/o description pin name i/o description 6 p81/exi1 i/o input port/output port / external interrupt scl i/o i 2 c synchronous clock input/output sck0 i/o ssio0 synchronous clock input/output 9 p82/exi2 i/o input port/output port / external interrupt ? ? ? sout0 o ssio0 data output 10 p83/exi3 i/o input port/output port / external interrupt ? ? ? ? ? ? 17 p84/exi4 i/o input port/output port / external interrupt ? ? ? sin1 i ssio1 data input 18 p85/exi5 i/o input port/output port / external interrupt ? ? ? sck1 i/o ssio1 synchronous clock input/output 26 p86/exi6 i/o input port/output port / external interrupt rxd0 i uart0 data input sout1 o ssio1 data output 27 p87/exi7 i/o input port/output port / external interrupt txd0 o uart0 data output ? ? ? note: the function which is not chosen is lost when either a secondary function or a tertiary function is chosen. however, when using it as an input, read-out of an input data is possible at a pnd
fedl610q304-01 ML610Q304 8/28 pin description in the i/o column, ??? denotes an input pin, ?i? an input pin, ?o? an output pin, and ?i/o? an input/output pin. pin name i/o description primary/ secondary/ tertiary logic power supply v ss ? negative power supply pin ? ? v dd ? positive power supply pin ? ? v ddl ? positive power supply pin for internal logic (internally generated) ? ? spv ss ? negative power supply pin for built-in speaker amplifier ? ? spv dd ? positive power supply pin for built-in speaker amplifier ? ? v ref ? reference power supply pin for successive-approximation type adc ? ? test test0 i/o input/output pin for testing. has a pull-down resistor built in. ? positive test1_n i input pin for testing. has a pull-up resistor built in. ? negative system reset_n i reset input pin . when this pin is set to a ? l ? level, the device is placed in system reset mode and the internal circuit is initialized. if after that this pin is set to a ? h ? level, program execution starts. this pin has a pull-up resistor built in. ? negative lsclk o low-speed clock output. this function is allocated to the secondary function of the p20 pin. secondary ? outclk o high-speed clock output. this function is allocated to the secondary function of the p21 pin. secondary ? general-purpose output port p20 to p22 o general-purpose output ports. provided with a secondary function. cannot be used as ports if their secondary function is used. primary positive general-purpose input/output port p40 to p42 i/o general-purpose input/output ports. provided with a tertiary function. cannot be used as ports if their tertiary function is used. primary positive p80 to p87 i/o general-purpose input/output ports. provided with a secondary function or a tertiary function. cannot be used as ports if their secondary function or tertiary function is used. primary positive
fedl610q304-01 ML610Q304 9/28 pin name i/o description primary/ secondary/ tertiary logic synchronous serial (ssio) sin0 i synchronous serial data input pin. allocated to the tertiary function of the p40 pin and p80 pin. tertiary positive sck0 i/o synchronous serial clock input/output pin. allocated to the tertiary function of the p41 pin and p81 pin. tertiary ? sout0 o synchronous serial data output pin. allocated to the tertiary function of the p42 pin and p82 pin. tertiary positive sin1 i synchronous serial data input pin. allocated to the tertiary function of the p84 pin. tertiary positive sck1 i/o synchronous serial clock input/output pin. allocated to the tertiary function of the p85 pin. tertiary ? sout1 o synchronous serial data output pin. allocated to the tertiary function of the p86 pin. tertiary positive i 2 c bus interface sda i/o i 2 c data input/output pin. this pin is used as the secondary function of the p80 pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull-up resistor. secondary positive scl i/o i 2 c clock output pin. this pin is used as the secondary function of the p81 pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull-up resistor. secondary positive uart txd0 o uart0 data output pin. allocated to the secondary function of the p87 pin. secondary positive rxd0 i uart0 data input pin. allocated to the the secondary function of the p86 pin. secondary positive external interrupt nmi i external non-maskable interrupt input pin. the interrupt occurs on both the rising and falling edges. primary positive/ negative exi0 to 7 i external maskable interrupt input pins. it is possible, for each bit, to specify whether the interrupt is enabled and select the interrupt edge by software. allocated to the primary function of the p80 to p87 pins. primary positive/ negative led drive led0 to 2 o pins for led driving. allocated to the primary function of the p20 to p22 pins. primary positive/ negative voice output function spp o positive output pin of the internal speaker amplifier. ? ? spm o negative output pin of the internal speaker amplifier. ? ? successive-approximation type a/d converter ain0 to 2 i analog inputs to ch0 to ch2 of the successive-approximation type a/d converter. allocated to the primary function of the p40 to p42 pins. primary positive/ negative
fedl610q304-01 ML610Q304 10/28 termination of unused pins how to terminate unused pins pin recommended pin termination reset_n open test0 open test1_n open v ref connect to v dd p40 to p42 (ain0 to ain2) open spv dd connect to v dd spv ss connect to v ss spp open spm open p20 to p22 open p80 to p87 open nmi open note: for unused input ports or unused input/output ports, if the corresponding pins are configured as high-impedance inputs and left open, the supply current may become excessively large. therefore, it is recommended to configure those pins as either inputs with a pull-down resistor/pull-up resistor or outputs.
fedl610q304-01 ML610Q304 11/28 electrical characteristics absolute maximum ratings (v ss = spv ss =0v) parameter symbol condition rating unit power supply voltage 1 v dd ta=25 c ? 0.3 to +7.0 v power supply voltage 2 spv dd ta=25 c ? 0.3 to +7.0 v power supply voltage 3 v ddl ta=25 c ? 0.3 to +3.6 v reference supply voltage v ref ta=25 c ? 0.3 to v dd +0.3 v input voltage v in ta=25 c ? 0.3 to v dd +0.3 v output voltage v out ta=25 c ? 0.3 to v dd +0.3 v output current 1 i out1 port 4,8, ta=25 c ? 12 to +11 ma output current 2 i out2 port 2, ta=25 c ? 12 to +20 ma power dissipation pd ta=25 c 1.0 w storage temperature t stg D ? 55 to +150 c recommended operating conditions (v ss = spv ss =0v) parameter symbol condition range unit operating temperature t op D ? 40 to +85 c v dd D 2.0 to 5.5 operating voltage spv dd D 2.0 to 5.5 v reference supply voltage v ref D 2.2 to v dd v operating frequency (cpu) v dd = 2.0 to 5.5v 27k to 4.2m hz f op v dd = 2.2 to 5.5v 4.2m to 8.4m capacitor externally connected to v ddl pin c l D 10 30% f
fedl610q304-01 ML610Q304 12/28 operating conditions of flash memory (v ss = spv ss =0v) parameter symbol condition range unit at write/erase (data flash area) -40 to +85 operating temperature t op at write/erase (program code area) 0 to +40 c operating voltage v dd at write/erase 2.2 to 5.5 v c epd data flash area(512byte x 4) 6,000 maximum rewrite count c epp program code area 100 cycles write cycles y dr D 10 years dc characteristics (1 of 5) (v dd = 2.0 to 5.5v, spv dd =2.0 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +85 c, unless otherwise specified) (1/5) rating parameter symbol condition min. typ. max. unit measuring circuit high-speed oscillation start time t xth D D 1.0 3.0 ms ta = ? 10 to +50c typ -1.5% typ +1.5% built-in rc oscillation frequency f lcr ta = ? 40 to +85c typ -3.0% 32.768 typ +3.0% khz ta = ? 10 to +50c typ -1.5% typ +1.5% source oscillation frequency f hpll ta = ? 40 to +85c typ -3.0% 4.098 or 8.192 typ +3.0% mhz 1 dc characteristics (2 of 5) (v dd = 2.0 to 5.5v, spv dd =2.0 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +85 c, unless otherwise specified) (2/5) rating parameter symbol condition min. typ. max. unit spm, spp output load resistance r lsp D 8 ? ? ? p spo1 spv dd =3.0v, f=1khz r spo =8 ? , thd 10% ? 0.45 ? w speaker amp output power p spo2 spv dd =5.0v, f=1khz r spo =8 ? , thd 10% ? 1.0 ? w
fedl610q304-01 ML610Q304 13/28 dc characteristics (3 of 5) (v dd = 2.0 to 5.5v, spv dd =2.0 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +85 c, unless otherwise specified) (3/5) rating parameter symbol condition min. typ. max. unit measuring circuit ta Q +50 c D 0.5 3.0 supply current 1 idd1 cpu: in stop state. high-speed oscillation: stopped ta Q +85 c D 0.5 8.0 ta Q +50 c D 2.7 5.0 supply current 2 idd2 cpu: in halt state (ltbc,wdt: operating) high-speed oscillation: stopped ta Q +85 c D 2.7 10 supply current 3 idd3 cpu: running at 32.768 khz* 1 high-speed oscillation: stopped D 20 30 a v dd =spv dd = 3.0v D 3.0 5.0 cpu: running at 4.096mhz cr oscillating mode v dd =spv dd = 5.0v D 3.0 5.0 v dd =spv dd = 3.0v D 4.0 6.0 supply current 4 idd4 cpu: running at 8.192mhz cr oscillating mode v dd =spv dd = 5.0v D 4.0 6.0 v dd =spv dd = 3.0v D 4.0 7.0 cpu: running at 4.096mhz cr oscillating mode during voice playback of 1khz,0db,sin-wave (no output load) v dd =spv dd = 5.0v D 6.0 10 v dd =spv dd = 3.0v D 5.0 8.0 supply current 5 idd5 cpu: running at 8.192mhz cr oscillating mode during voice playback of 1khz,0db,sin-wave (no output load) v dd =spv dd = 5.0v D 7.0 11 ma 1 *1: case when the cpu operating rate is 100% (no halt state).
fedl610q304-01 ML610Q304 14/28 dc characteristics (4 of 5) (v dd = 2.0 to 5.5v, spv dd =2.0 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +85 c, unless otherwise specified) (4/5) rating parameter symbol condition min. typ. max. unit measuring circuit voh1 ioh1= ? 0.5ma v dd ? 0.5 D D output voltage 1 (p20 to p22) (p40 to p42) (p80 to p87) vol1 iol1=+0.5ma D D 0.5 iol2=+5ma v dd R 2.2v D D 0.5 output voltage 2 (p20 to p22) vol2 (when led drive mode is selected) iol2=+8ma v dd R 2.3v D D 0.5 output voltage 3 (p80 to p81) vol3 iol3=+3ma ( i 2 c bus input/output mode) D D 0.4 v 2 iooh voh=v dd (in high-impedance state) D D 1.0 output leakage (p20 to p22) (p40 to p42) (p80 to p87) iool vol=v ss (in high-impedance state) ? 1.0 D D a 3 iih1 vih1=v dd 0 D 1.0 input current 1 (reset_n) (test1_n) iil1 vil1=v ss ? 1500 ? 300 ? 20 iih2 vih2=v dd (when pulled-down) 2 30 250 iil2 vil2=v ss (when pulled-up) ?2 50 ? 30 ? 2 iih2z vih2=v dd (in high-impedance state) D D 1.0 input current 2 (nmi) (p40 to p42) (p80 to p87) iil2z vil2=v ss (in high-impedance state) ? 1.0 D D iih3 vih3=v dd 20 300 1500 input current 3 (test0) iil3 vil3=v ss ? 1.0 D D a 4
fedl610q304-01 ML610Q304 15/28 dc characteristics (5 of 5) (v dd = 2.0 to 5.5v, spv dd =2.0 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +85 c, unless otherwise specified) (5/5) rating parameter symbol condition min. typ. max. unit measuring circuit vih1 D 0.7 v dd D v dd input voltage 1 (reset_n) (test0) (test1_n) (nmi) (p40 to p42) (p80 to p87) vil1 D 0 D 0.3 v dd hysteresis width (reset_n) (test0) (test1_n) (nmi) (p40 to p42) (p80 to p87) S vt D 0.05 v dd D 0.4 v dd v 5 input pin capacitance (nmi) (p40 to p42) (p80 to p87) cin f=10khz v rms =50mv ta=25 c D D 10 pf D hysteresis width S v t input signal internal signal v dd v ss v ss v ddl
fedl610q304-01 ML610Q304 16/28 measuring circuits ? measuring circuit 1 ? measuring circuit 2 a v dd v ref c sv c av v ss spv ss c v 0.1f c sv 0.1f c av 1.0f c l 10f c v spv dd v ddl c l a input pins v v dd v ss v ddl spv ss vih vil output pins (* 1) input logic circuit to determine the specified measuring conditions. (* 2) measured at the specified output pins. (* 2) (* 1) v ref spv dd
fedl610q304-01 ML610Q304 17/28 ? measuring circuit 3 ? measuring circuit 4 ? measuring circuit 5 input pins a v dd v ss v ddl spv ss vih vil output pins (* 1) input logic circuit to determine the specified measuring conditions. (* 2) measured at the specified output pins. (* 2) v ref spv dd (* 1) input pins a v dd v ddl spv ss output pins (* 3) measured at the specified output pins. (* 3) v ss v ref spv dd input pins v dd v ddl spv ss vih vil output pins (* 1) input logic circuit to determine the specified measuring conditions. (* 1) waveform monitoring v ss v ref spv dd
fedl610q304-01 ML610Q304 18/28 ac characteristics (reset) ? reset (v dd = 2.0 to 5.5v, spv dd =2.0 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +85 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit time until it starts spvdd after starting vdd t vdd D 0 D D ns reset pulse width p rst D 100 D D reset noise elimination pulse width p nrst D D D 0.4 s power-on reset activation power rise time t por D D D 10 ms 1 reset_n reset_n pin reset v dd 0.9 v dd 0.1 v dd t por power on reset p rst vil1 vil1
fedl610q304-01 ML610Q304 19/28 ? ac characteristics (oscillation stable time after stop release) (v dd = 2.0 to 5.5v, spv dd =2.0 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +85 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit oscillation stable time after stop release t pup1 D 2 D D ms ? ac characteristics (external interrupt) (v dd = 2.0 to 5.5v, spv dd =2.0 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +85 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit external interrupt disable period t nul interrupt: enabled (mie=1) cpu: nop operation 2.5 sysclk D 3.5 sysclk s t nul p80 to p87 (rising-edge interrupt) p80 to p87 (falling-edge interrupt) nmi, p80 to p87 (both-edge interrupt) t nul t nul high-speed oscillation waveform osclk, hsclk stop mode high-speed oscillation waveform program operation mode osclk, hsclk waveform osclk, hsclk waveform t pup1 high-speed oscillation waveform sysclk hsclk waveform hsclk waveform interruput request program operation mode
fedl610q304-01 ML610Q304 20/28 ? ac characteristics (synchronous serial port) (v dd = 2.0 to 5.5v, spv dd =2.0 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +85 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit when high-speed oscillation is not active 10 D D s sclk input cycle (slave mode) t scyc when high-speed oscillation is active 500 D D ns vdd R 2.4v D 4 D sclk output cycle (master mode) t scyc vdd R 2.0v D 2 D mhz when high-speed oscillation is not active 4 D D s sclk input pulse width (slave mode) t sw when high-speed oscillation is active 200 D D ns sclk output pulse width (master mode) t sw D sclk* 1 0.4 sclk* 1 0.5 sclk* 1 0.6 s sout output delay time (slave mode) t sd D D D 180 ns sout output delay time (master mode) t sd D D D 80 ns sin input setup time (slave mode) t ss D 50 D D ns sin input hold time t sh D 50 D D ns *1: clock period selected with s0ck3?0 of the serial port 0 mode register (sio0mod1) t sd sck0* sin0* sout0* *: indicates the secondary function of the port. t sd t ss t sh t sw t sw t scyc
fedl610q304-01 ML610Q304 21/28 ? ac characteristics (i 2 c bus interface: standard mode 100khz) (v dd = 2.0 to 5.5v, spv dd =2.0 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +85 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit scl clock frequency f scl ? 0 ? 100 khz scl hold time (start/restart condition) t hd:sta ? 4.0 ? ? s scl ?l? level time t low ? 4.7 ? ? s scl ?h? level time t high ? 4.0 ? ? s scl setup time (restart condition) t su:sta ? 4.7 ? ? s sda hold time t hd:dat ? 0 ? ? s sda setup time t su:dat ? 0.25 ? ? s sda setup time (stop condition) t su:sto ? 4.0 ? ? s bus-free time t buf ? 4.7 ? ? s ? ac characteristics (i 2 c bus interface: fast mode 400khz) (v dd = 2.0 to 5.5v, spv dd =2.0 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +85 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit scl clock frequency f scl ? 0 ? 400 khz scl hold time (start/restart condition) t hd:sta ? 0.6 ? ? s scl ?l? level time t low ? 1.3 ? ? s scl ?h? level time t high ? 0.6 ? ? s scl setup time (restart condition) t su:sta ? 0.6 ? ? s sda hold time t hd:dat ? 0 ? ? s sda setup time t su:dat ? 0.1 ? ? s sda setup time (stop condition) t su:sto ? 0.6 ? ? s bus-free time t buf ? 1.3 ? ? s p81/scl p80/sda start condition restart condition stop condition t buf t hd:sta t low t high t su:sta t hd:sta t su:dat t hd:dat t su:sto
fedl610q304-01 ML610Q304 22/28 electrical characteristics of successive approximation type a/d converter (dv dd =spv dd =2.2 to 5.5v, v ref =2.2 to 5.5v, v ss =spv ss =0v, ta= ? 40 to +85 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit resolution n D D D 10 bit 2.7v Q v ref Q 5.5v ? 4 D +4 integral non-linearity error idl 2.2v Q v ref Q 2.7v ? 5 D +5 2.7v Q v ref Q 5.5v ? 3 D +3 differential non-linearity error dnl 2.2v Q v ref Q 2.7v ?4 D +4 zero-scale error v off r i Q 5k ? 4 D +4 full-scale error fse r i Q 5k ? 4 D +4 lsb input impedance r i D D D 5k reference supply voltage v ref D 2.2 v dd v conversion time t conv hsclk=4m to 8.4mhz D 102 D /ch : period of high-speed clock (hsclk) a v dd v ddl v ss 10f ? ri Q 5k ?
fedl610q304-01 ML610Q304 23/28 power-on/shutdown sequence ? when the power rise time is 10 ms or less ? when the power rise time is more than 10 ms recommended power-on/shutdown sequence 1 turn on v dd and spv dd simultaneously, or turn on spv dd after turning on v dd . 2 turn off v dd and spv dd simultaneously, or turn off v dd after turning on spv dd . upon power-on upon shutdown 0v v dd spv dd t vdd 0v upon power-on upon shutdown 0v reset_n 0v v dd spv dd 10 ms (min.) 90% vil t vdd 90%
fedl610q304-01 ML610Q304 24/28 example of application circuit c v : 0.1uf c l : 10uf c av : 1uf c sv : 0.1uf test1_n v dd v ss v ss v ref led p20 to p22 c v c av test0 supply voltage ML610Q304 uvdd_o vt ref reset_n test v ss uease i/f nmi speaker spp spm spv dd spv ss c sv v ddl c l p40/ain0 to p42/ain2 reset_n analog p87 p86 rxd0 txd0
fedl610q304-01 ML610Q304 25/28 package dimensions notes for mounting the surface mount type package the surface mount type packages are very susceptible to h eat in reflow mounting and hum idity absorbed in storage. therefore, before you perform reflow mounting, contact our responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). the heat resistance (example) of this lsi is shown below. heat resistance ( ja) changes with the size and the number of layers of a substrate. pcb w/l/t=60 / 62 / 1.6 mm pcb layer 1 layers air cooling conditions calm 0m/sec heat resistance ja 56.6[ /w]( back diepad contact) power consumption of chip pmax 0.351[w] tjmax of this lsi is 125 . tjmax is expressed with the following formulas. tjmax = tamax + ja pmax [unit:mm]
fedl610q304-01 ML610Q304 26/28 figure pf soldering department terminal existence range attention of the layout of a mounting board please take into consideration enough that there are not ease of a mounting, the reliability of contact, leading about of a wiring, and a solder bridge generate in the case of layout of the foot pattern of a mounting board. the optimal layout of a foot pattern changes by the board quality of material, the solder paste category to be used, thickness, the soldering methodology, etc. therefore, since th e span where the terminator of this package may exist is shown as a "soldering part terminator extent drawing", please give as reference data of a foot pattern design. reference drawing [unit:mm]
fedl610q304-01 ML610Q304 27/28 revision history page document no. date previous edition current edition description fedl610q304-01 jul 16,2014 D D final edition 1
fedl610q304-01 ML610Q304 28/28 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. examples of application circuits, circuit constants and any othe r information contained herein illustrate the standard usage an d operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circui ts for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communicatio n devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of h uman injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controlle r or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2014 lapis semiconductor co., ltd. 2-4-8 shinyokohama, kouhoku-ku, yokohama 222-8575, japan http://www.lapis-semi.com/en/

▲Up To Search▲

Price & Availability of ML610Q304

	To Download ML610Q304 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .